Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
196 Order Number: 329679-001US
The Intel
®
Quark SoC X1000 Core asserts BREQ when it requires control of the bus.
BREQ notifies the arbitration logic that the processor has pending bus activity and
requests the bus. When its HOLD input is inactive and its HLDA signal is deasserted,
the Intel
®
Quark SoC X1000 Core can acquire the bus. Otherwise if HOLD is asserted,
then the Intel
®
Quark SoC X1000 Core has to wait for HOLD to be deasserted before
acquiring the bus. If the Intel
®
Quark SoC X1000 Core does not have the bus, then its
address, data, and status pins are 3-stated. However, the processor can execute
instructions out of the internal cache or instruction queue, and does not need control of
the bus to remain active.
The address buses shown in Figure 84 and Figure 85 are bidirectional to allow cache
invalidations to the processors during memory writes on the bus.
10.3 Bus Functional Description
The Intel
®
Quark SoC X1000 Core supports a wide variety of bus transfers to meet the
needs of high performance systems. Bus transfers can be single cycle or multiple cycle,
burst or non-burst, cacheable or non-cacheable, 8-, 16- or 32-bit, and pseudo-locked.
Cache invalidation cycles and locked cycles provide support for multiprocessor systems.
This section explains basic non-cacheable, non-burst single cycle transfers. It also
details multiple cycle transfers and introduces the burst mode. Cacheability is
introduced in Section 10.3.3. The remaining sections describe locked, pseudo-locked,
invalidate, bus hold, and interrupt cycles.
Bus cycles and data cycles are discussed in this section. A bus cycle is at least two
clocks long and begins with ADS# asserted in the first clock and RDY# or BRDY#
asserted in the last clock. Data is transferred to or from the Intel
®
Quark SoC X1000
Core during a data cycle. A bus cycle contains one or more data cycles.
Refer to Section 10.3.13 for a description of the bus states shown in the timing
diagrams.
10.3.1 Non-Cacheable Non-Burst Single Cycles
10.3.1.1 No Wait States
The fastest non-burst bus cycle that the Intel
®
Quark SoC X1000 Core supports is two
clocks. These cycles are called 2-2 cycles because reads and writes take two cycles
each. The first “2” refers to reads and the second “2” to writes. If a wait state needs to
be added to the write, the cycle is called “2-3.”
Basic two-clock read and write cycles are shown in Figure 86. The Intel
®
Quark SoC
X1000 Core initiates a cycle by asserting the address status signal (ADS#) at the rising
edge of the first clock. The ADS# output indicates that a valid bus cycle definition and
address is available on the cycle definition lines and address bus.