Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
198 Order Number: 329679-001US
Figure 87. Basic 3-3 Bus Cycle
The burst ready input (BRDY#) must be deasserted on all clock edges where RDY# is
deasserted for proper operation of these simple non-burst cycles.
10.3.2 Multiple and Burst Cycle Bus Transfers
Multiple cycle bus transfers can be caused by internal requests from the Intel
®
Quark
SoC X1000 Core or by the external memory system. An internal request for a 128-bit
pre-fetch requires more than one cycle. Internal requests for unaligned data may also
require multiple bus cycles. A cache line fill requires multiple cycles to complete.
The external system can cause a multiple cycle transfer when it can only supply 8- or
16-bits per cycle.
Only multiple cycle transfers caused by internal requests are considered in this section.
Cacheable cycles and 8- and 16-bit transfers are covered in Section 10.3.3 and
Section 10.3.5.
An internal request by the Intel
®
Quark SoC X1000 Core for a 64-bit floating-point load
must take more than one internal cycle.
10.3.2.1 Burst Cycles
The Intel
®
Quark SoC X1000 Core can accept burst cycles for any bus requests that
require more than a single data cycle. During burst cycles, a new data item is strobed
into the Intel
®
Quark SoC X1000 Core every clock rather than every other clock as in
non-burst cycles. The fastest burst cycle requires two clocks for the first data item, with
subsequent data items returned every clock.
The Intel
®
Quark SoC X1000 Core is capable of bursting a maximum of 32 bits during a
write. Burst writes can only occur if BS8# or BS16# is asserted. For example, the
Intel
®
Quark SoC X1000 Core can burst write four 8-bit operands or two 16-bit
operands in a single burst cycle. But the Intel
®
Quark SoC X1000 Core cannot burst
multiple 32-bit writes in a single burst cycle.
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
BLAST#
DATA
Ti T1 T2 Ti
Read Write
To Processor
From Processor
T2 T1 T2 T2
‡
†
†
‡
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