Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
200 Order Number: 329679-001US
10.3.2.3 Non-Cacheable, Non-Burst, Multiple Cycle Transfers
Figure 88 illustrates a two-cycle, non-burst, non-cacheable read. This transfer is simply
a sequence of two single cycle transfers. The Intel
®
Quark SoC X1000 Core indicates to
the external system that this is a multiple cycle transfer by deasserting BLAST# during
the second clock of the first cycle. The external system asserts RDY# to indicate that it
will not burst the data. The external system also indicates that the data is not
cacheable by deasserting KEN# one clock before it asserts RDY#. When the Intel
®
Quark SoC X1000 Core samples RDY# asserted, it ignores BRDY#.
Figure 88. Non-Cacheable, Non-Burst, Multiple-Cycle Transfers
Each cycle in the transfer begins when ADS# is asserted and the cycle is complete
when the external system asserts RDY#.
The Intel
®
Quark SoC X1000 Core indicates the last cycle of the transfer by asserting
BLAST#. The next RDY# asserted by the external system terminates the transfer.
10.3.2.4 Non-Cacheable Burst Cycles
The external system converts a multiple cycle request into a burst cycle by asserting
BRDY# rather than RDY# in the first cycle of the transfer. This is illustrated in
Figure 89.
There are several features to note in the burst read. ADS# is asserted only during the
first cycle of the transfer. RDY# must be deasserted when BRDY# is asserted.
BLAST# behaves exactly as it does in the non-burst read. BLAST# is deasserted in the
second clock of the first cycle of the transfer, indicating more cycles to follow. In the
last cycle, BLAST# is asserted, prompting the external memory system to end the
burst after asserting the next BRDY#.
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
BE3#–BE0#
RDY#
BRDY#
BLAST#
DATA
To Processor
†
KEN#
2nd Data
TiT2T1T2T1Ti
1st Data
†
†
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