Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 201
Bus Operation—Intel
®
Quark Core
Figure 89. Non-Cacheable Burst Cycle
10.3.3 Cacheable Cycles
Any memory read can become a cache fill operation. The external memory system can
allow a read request to fill a cache line by asserting KEN# one clock before RDY# or
BRDY# during the first cycle of the transfer on the external bus. Once KEN# is asserted
and the remaining three requirements described below are met, the Intel
®
Quark SoC
X1000 Core fetches an entire cache line regardless of the state of KEN#. KEN# must be
asserted in the last cycle of the transfer for the data to be written into the internal
cache. The Intel
®
Quark SoC X1000 Core converts only memory reads or prefetches
into a cache fill.
KEN# is ignored during write or I/O cycles. Memory writes are stored only in the on-
chip cache if there is a cache hit. I/O space is never cached in the internal cache.
To transform a read or a prefetch into a cache line fill, the following conditions must be
met:
1. The KEN# pin must be asserted one clock prior to RDY# or BRDY# being asserted
for the first data cycle.
2. The cycle must be of a type that can be internally cached. (Locked reads, I/O
reads, and interrupt acknowledge cycles are never cached.)
3. The page table entry must have the page cache disable bit (PCD) set to 0. To cache
a page table entry, the page directory must have PCD=0. To cache reads or
prefetches when paging is disabled, or to cache the page directory entry, control
register 3 (CR3) must have PCD=0.
4. The cache disable (CD) bit in control register 0 (CR0) must be clear.
External hardware can determine when the Intel
®
Quark SoC X1000 Core has
transformed a read or prefetch into a cache fill by examining the KEN#, M/IO#, D/C#,
W/R#, LOCK#, and PCD pins. These pins convey to the system the outcome of
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
BE3#–BE0#
RDY#
BRDY#
BLAST#
DATA
KEN#
TiT2T1T2T1Ti
To Processor
†
†
†
242202-034