Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
202 Order Number: 329679-001US
conditions 1–3 in the above list. In addition, the Intel
®
Quark SoC X1000 Core drives
PCD high whenever the CD bit in CR0 is set, so that external hardware can evaluate
condition 4.
Cacheable cycles can be burst or non-burst.
10.3.3.1 Byte Enables during a Cache Line Fill
For the first cycle in the line fill, the state of the byte enables should be ignored. In a
non-cacheable memory read, the byte enables indicate the bytes actually required by
the memory or code fetch.
The Intel
®
Quark SoC X1000 Core expects to receive valid data on its entire bus (32
bits) in the first cycle of a cache line fill. Data should be returned with the assumption
that all the byte enable pins are asserted. However if BS8# is asserted, only one byte
should be returned on data lines D[7:0]. Similarly if BS16# is asserted, two bytes
should be returned on D[15:0].
The Intel
®
Quark SoC X1000 Core generates the addresses and byte enables for all
subsequent cycles in the line fill. The order in which data is read during a line fill
depends on the address of the first item read. Byte ordering is discussed in
Section 10.3.4.
10.3.3.2 Non-Burst Cacheable Cycles
Figure 90 shows a non-burst cacheable cycle. The cycle becomes a cache fill when the
Intel
®
Quark SoC X1000 Core samples KEN# asserted at the end of the first clock. The
Intel
®
Quark SoC X1000 Core deasserts BLAST# in the second clock in response to
KEN#. BLAST# is deasserted because a cache fill requires three additional cycles to
complete. BLAST# remains deasserted until the last transfer in the cache line fill. KEN#
must be asserted in the last cycle of the transfer for the data to be written into the
internal cache.
Note that this cycle would be a single bus cycle if KEN# was not sampled asserted at
the end of the first clock. The subsequent three reads would not have happened since a
cache fill was not requested.
The BLAST# output is invalid in the first clock of a cycle. BLAST# may be asserted
during the first clock due to earlier inputs. Ignore BLAST# until the second clock.
During the first cycle of the cache line fill the external system should treat the byte
enables as if they are all asserted. In subsequent cycles in the burst, the Intel
®
Quark
SoC X1000 Core drives the address lines and byte enables. (See Section 10.3.4.2.)