Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 205
Bus Operation—Intel
®
Quark Core
Figure 92. Effect of Changing KEN#
10.3.4 Burst Mode Details
10.3.4.1 Adding Wait States to Burst Cycles
Burst cycles need not return data on every clock. The Intel
®
Quark SoC X1000 Core
strobes data into the chip only when either RDY# or BRDY# is asserted. Deasserting
BRDY# and RDY# adds a wait state to the transfer. A burst cycle where two clocks are
required for every burst item is shown in Figure 93.
242202-037
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
RDY#
BLAST#
DATA
Ti T1 T2 T2
To Processor
T2 T2 T1 T2
A3–A2
BE3#–BE0#
KEN#
†
††