Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
206 Order Number: 329679-001US
Figure 93. Slow Burst Cycle
10.3.4.2 Burst and Cache Line Fill Order
The burst order used by the Intel
®
Quark SoC X1000 Core is shown in Table 67. This
burst order is followed by any burst cycle (cache or not), cache line fill (burst or not) or
code prefetch.
The Intel
®
Quark SoC X1000 Core presents each request for data in an order
determined by the first address in the transfer. For example, if the first address was
104 the next three addresses in the burst will be 100, 10C and 108. An example of
burst address sequencing is shown in Figure 94.
242202-038
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
KEN#
RDY#
BLAST#
DATA
Ti T1 T2 T2 T2 T2 T2 T2 T2 T2
To Processor
BRDY#
A3–A2
BE3#–BE0#
†
†
†
††
Table 67. Burst Order (Both Read and Write Bursts)
First Address Second Address Third Address Fourth Address
048C
40C8
8C04
C840