Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
210 Order Number: 329679-001US
Figure 97. 8-Bit Bus Size Cycle
Extra cycles forced by BS16# and BS8# signals should be viewed as independent bus
cycles. BS16# and BS8# should be asserted for each additional cycle unless the
addressed device can change the number of bytes it can return between cycles. The
Intel
®
Quark SoC X1000 Core deasserts BLAST# until the last cycle before the transfer
is complete.
Refer to Section 10.1.2 for the sequencing of addresses when BS8# or BS16# are
asserted.
During burst cycles, BS8# and BS16# operate in the same manner as during non-burst
cycles. For example, a single non-cacheable read could be transferred by the Intel
®
Quark SoC X1000 Core as four 8-bit burst data cycles. Similarly, a single 32-bit write
could be written as four 8-bit burst data cycles. An example of a burst write is shown in
Figure 98. Burst writes can only occur if BS8# or BS16# is asserted.
242202-069
CLK
ADS#
A31–A2
M/IO#
D/C#
W/R#
RDY#
BLAST#
DATA
Ti T1 T2 Ti
To Processor
T1 T2 T1 T2
BS8#
BE3#–BE0#
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