Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 213
Bus Operation—Intel
®
Quark Core
PLOCK# can change several times during a cycle, settling to its final value in the clock
in which RDY# is asserted.
10.3.7.1 Floating-Point Read and Write Cycles
For Intel
®
Quark SoC X1000 Core, 64-bit floating-point read and write cycles are also
examples of operand transfers that take more than one bus cycle.
Figure 100. Pseudo Lock Timing
10.3.8 Invalidate Cycles
Invalidate cycles keep the Intel
®
Quark SoC X1000 Core internal cache contents
consistent with external memory. The Intel
®
Quark SoC X1000 Core contains a
mechanism for monitoring writes by other devices to external memory. When the
Intel
®
Quark SoC X1000 Core finds a write to a section of external memory contained
in its internal cache, the Intel
®
Quark SoC X1000 Core's internal copy is invalidated.
Invalidations use two pins, address hold request (AHOLD) and valid external address
(EADS#). There are two steps in an invalidation cycle. First, the external system
asserts the AHOLD input forcing the Intel
®
Quark SoC X1000 Core to immediately
relinquish its address bus. Next, the external system asserts EADS#, indicating that a
valid address is on the Intel
®
Quark SoC X1000 Core address bus. Figure 101 shows
the fastest possible invalidation cycle. The Intel
®
Quark SoC X1000 Core recognizes
AHOLD on one CLK edge and floats the address bus in response. To allow the address
bus to float and avoid contention, EADS# and the invalidation address should not be
driven until the following CLK edge. The Intel
®
Quark SoC X1000 Core reads the
address over its address lines. If the Intel
®
Quark SoC X1000 Core finds this address in
its internal cache, the cache entry is invalidated. Note that the Intel
®
Quark SoC X1000
Core address bus is input/output.
TiT2T1T2T1Ti
CLK
ADS#
A31–A2
M/IO#
D/C#
BE3#–BE0#
W/R#
RDY#
BLAST#
From Processor
DATA
PLOCK#
Write Write
‡
‡
‡
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