Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 215
Bus Operation—Intel
®
Quark Core
10.3.8.1 Rate of Invalidate Cycles
The Intel
®
Quark SoC X1000 Core can accept one invalidate per clock except in the last
clock of a line fill. One invalidate per clock is possible as long as EADS# is deasserted in
ONE or BOTH of the following cases:
1. In the clock in which RDY# or BRDY# is asserted for the last time.
2. In the clock following the clock in which RDY# or BRDY# is asserted for the last
time.
This definition allows two system designs. Simple designs can restrict invalidates to one
every other clock. The simple design need not track bus activity. Alternatively, systems
can request one invalidate per clock provided that the bus is monitored.
10.3.8.2 Running Invalidate Cycles Concurrently with Line Fills
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not support
second-level cache.
Precautions are necessary to avoid caching stale data in the Intel
®
Quark SoC X1000
Core cache in a system with a second-level cache. An example of a system with a
second-level cache is shown in Figure 103.
An external device can write to main memory over the system bus while the Intel
®
Quark SoC X1000 Core is retrieving data from the second-level cache. The Intel
®
Quark SoC X1000 Core must invalidate a line in its internal cache if the external device
is writing to a main memory address that is also contained in the Intel
®
Quark SoC
X1000 Core cache.
A potential problem exists if the external device is writing to an address in external
memory, and at the same time the Intel
®
Quark SoC X1000 Core is reading data from
the same address in the second-level cache. The system must force an invalidation
cycle to invalidate the data that the Intel
®
Quark SoC X1000 Core has requested during
the line fill.