Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 217
Bus Operation—Intel
®
Quark Core
Figure 104. Cache Invalidation Cycle Concurrent with Line Fill
10.3.9 Bus Hold
The Intel
®
Quark SoC X1000 Core provides a bus hold, hold acknowledge protocol
using the bus hold request (HOLD) and bus hold acknowledge (HLDA) pins. Asserting
the HOLD input indicates that another bus master has requested control of the Intel
®
Quark SoC X1000 Core bus. The Intel
®
Quark SoC X1000 Core responds by floating its
bus and asserting HLDA when the current bus cycle, or sequence of locked cycles, is
complete. An example of a HOLD/HLDA transaction is shown in Figure 105. The Intel
®
Quark SoC X1000 Core can respond to HOLD by floating its bus and asserting HLDA
while RESET is asserted.
242202-093
NOTES:
1. Data returned must be consistent if its address equals the invalidation address in this clock.
2. Data returned is not cached if its address equals the invalidation address in this clock.
CLK
ADS#
ADDR
AHOLD
RDY#
DATA
Ti T1 T2 T2 T2 T2 T2 T2 Ti
To Processor
EADS#
12
BRDY#
KEN#
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