Specifications

Intel
®
Quark Core—Architectural Overview
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
22 Order Number: 329679-001US
3.0 Architectural Overview
3.1 Internal Architecture
The Intel
®
Quark Core has a 32-bit architecture with on-chip memory management
and cache and floating-point units. The Intel
®
Quark Core also supports dynamic bus
sizing for the external data bus; that is, the bus size can be specified as 8-, 16-, or 32-
bits wide.
Note: The implementation of Intel
®
Quark Core on Intel
®
Quark SoC X1000 does not support
dynamic bus sizing. Bus width is fixed at 32 bits.
Intel
®
Quark Core functional units are listed below:
• Bus Interface Unit (BIU)
•Cache Unit
• Instruction Prefetch Unit
• Instruction Decode Unit
• Control Unit
• Integer (Datapath) Unit
• Floating-Point Unit
• Segmentation Unit
• Paging Unit
For further details, see Chapter 3 in the Intel
®
Quark SoC X1000 Core Hardware
Reference Manual.
3.2 System Architecture
Intel
®
Quark Core System Architecture includes the following:
• Memory Organization
• I/O Space
• Addressing Modes
• Data Types
• Interrupts
3.3 Memory Organization
Memory on the Intel
®
Quark SoC X1000 Core is divided up into 8-bit quantities (bytes),
16-bit quantities (words), and 32-bit quantities (dwords). Words are stored in two
consecutive bytes in memory with the low-order byte at the lowest address, the high
order byte at the high address. Dwords are stored in four consecutive bytes in memory
with the low-order byte at the lowest address, the high-order byte at the highest
address. The address of a word or dword is the byte address of the low-order byte.