Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
224 Order Number: 329679-001US
10.3.13 Bus States
A bus state diagram is shown in Figure 111. A description of the signals used in the
diagram is given in Table 69.
Figure 111. Bus State Diagram
240950–069
Ti
T1 T2
T1b
T
b
Request Pending
·
HOLD Deasserted
·
AHOLD Deasserted
·
BOFF# Deasserted
(BRDY# · BLAST#) Asserted)
·
HOLD Deasserted
·
AHOLD Deasserted
·
BOFF# Deasserted
AHOLD Deasserted
·
BOFF# Deasserted
·
(HOLD) Deasserted
†
(RDY# Asserted + (BRDY# · BLAST#) Asserted)
·
(HOLD + AHOLD + No Request)
·
BOFF# Deasserted
Request Pending
·
(RDY# Asserted +
B
O
F
F
#
A
s
s
e
r
t
e
d
BOFF#
Deasserted
BOFF#
Asserted
BOFF# Deasserted
BOFF# Asserted
† HOLD is only factored into this state transition if Tb was
entered while a non-cacheable. non-burst, code prefetch was
in progress. Otherwise, ignore HOLD.
Table 69. Bus State Description
State Means
Ti
Bus is idle. Address and status signals may be driven to undefined values, or the bus may be
floated to a high impedance state.
T1 First clock cycle of a bus cycle. Valid address and status are driven and ADS# is asserted.
T2
Second and subsequent clock cycles of a bus cycle. Data is driven if the cycle is a write, or data is
expected if the cycle is a read. RDY# and BRDY# are sampled.
T1b First clock cycle of a restarted bus cycle. Valid address and status are driven and ADS# is asserted.
Tb Second and subsequent clock cycles of an aborted bus cycle.