Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 227
Bus Operation—Intel
®
Quark Core
2. Four signals: INV, WB/WT#, HITM#, and CACHE#, support the write-back
operation of the internal cache.
3. The SRESET signal does not write back, invalidate, or disable the cache. Special
test modes are also not initiated through SRESET.
4. The FLUSH# signal behaves the same as the WBINVD instruction. Upon assertion,
FLUSH# writes back all modified lines, invalidates the cache, and issues two special
bus cycles.
5. The PLOCK# signal remains deasserted.
10.4.2 Burst Cycles
Figure 112 shows a basic burst read cycle of the Write-Back Enhanced Intel
®
Quark
SoC X1000 Core. In the Enhanced Bus mode, both PCD and CACHE# are asserted if the
cycle is internally cacheable. The Write-Back Enhanced Intel
®
Quark SoC X1000 Core
samples KEN# in the clock before the first BRDY#. If KEN# is asserted by the system,
this cycle is transformed into a multiple-transfer cycle. With each data item returned
from external memory, the data is “cached” only if KEN# is asserted again in the clock
before the last BRDY# signal. Data is sampled only in the clock in which BRDY# is
asserted. If the data is not sent to the processor every clock, it causes a “slow burst”
cycle.
Figure 112. Basic Burst Read Cycle
10.4.2.1 Non-Cacheable Burst Operation
When CACHE# is asserted on a read cycle, the processor follows with BLAST# high
when KEN# is asserted. However, the converse is not true. The Write-Back Enhanced
Intel
®
Quark SoC X1000 Core may elect to read burst data that are identified as non-
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CLK
ADS#
A31–A4
M/IO#
D/C#
W/R#
A3–A2
BLAST#
CACHE#
BRDY#
WB/WT#
12345678910111213
PCD
KEN#
0 4 8 C