Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
228 Order Number: 329679-001US
cacheable by either CACHE# or KEN#. In this case, BLAST# is also high in the same
cycle as the first BRDY# (in clock four). To improve performance, the memory
controller should try to complete the cycle as a burst cycle.
The assertion of CACHE# on a write cycle signifies a replacement or snoop write-back
cycle. These cycles consist of four doubleword transfers (either bursts or non-burst).
The signals KEN# and WB/WT# are not sampled during write-back cycles because the
processor does not attempt to redefine the cacheability of the line.
10.4.2.2 Burst Cycle Signal Protocol
The signals from ADS# through BLAST#, which are shown in Figure 112, have the
same function and timing in both Standard Bus and Enhanced Bus modes. Burst cycles
can be up to 16-bytes long (four aligned doublewords) and can start with any one of
the four doublewords. The sequence of the addresses is determined by the first address
and the sequence follows the order shown in Table 67. The burst order for reads is the
same as the burst order for writes. (See Section 10.3.4.2.)
An attempted line fill caused by a read miss is indicated by the assertion of CACHE#
and W/R#. For a line fill to occur, the system must assert KEN# twice: one clock prior
to the first BRDY# and one clock prior to last BRDY#. It takes only one deassertion of
KEN# to mark the line as non-cacheable. A write-back cycle of a cache line, due to
replacement or snoop, is indicated by the assertion of CACHE# low and W/R# high.
KEN# has no effect during write-back cycles. CACHE# is valid from the assertion of
ADS# through the clock in which the first RDY# or BRDY# is asserted. CACHE# is
deasserted at all other times. PCD behaves the same in Enhanced Bus mode as in
Standard Bus mode, except that it is low during write-back cycles.
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core samples WB/WT# once, in the
same clock as the first BRDY#. This sampled value of WB/WT# is combined with PWT
to bring the line into the internal cache, either as a write-back line or write-through
line.
10.4.3 Cache Consistency Cycles
The system performs snooping to maintain cache consistency. Snoop cycles can be
performed under AHOLD, BOFF#, or HOLD, as described in Table 70.
The snoop cycle begins by checking whether a particular cache line has been “cached”
and invalidates the line based on the state of the INV pin. If the Write-Back Enhanced
Intel
®
Quark SoC X1000 Core is configured in Enhanced Bus mode, the system must
drive INV high to invalidate a particular cache line. The Write-Back Enhanced Intel
®
Quark SoC X1000 Core does not have an output pin to indicate a snoop hit to an S-
state line or an E-state line. However, the Write-Back Enhanced Intel
®
Quark SoC
Table 70. Snoop Cycles under AHOLD, BOFF#, or HOLD
AHOLD
Floats the address bus. ADS# is asserted under AHOLD only to initiate a snoop write-back cycle.
An ongoing burst cycle is completed under AHOLD. For non-burst cycles, a specific non-burst
transfer (ADS#-RDY# transfer) is completed under AHOLD and fractured before the next
assertion of ADS#. A snoop write-back cycle is reordered ahead of a fractured non-burst cycle
and the non-burst cycle is completed only after the snoop write-back cycle is completed,
provided there are no other snoop write-back cycles scheduled.
BOFF#
Overrides AHOLD and takes effect in the next clock. On-going bus cycles will stop in the clock
following the assertion of BOFF# and resume when BOFF# is de-asserted. The snoop write-back
cycle begins after BOFF# is de-asserted followed by the backed-off cycle.
HOLD
HOLD is acknowledged only between bus cycles, except for a non-cacheable, non-burst code
prefetch cycle. In a non-cacheable, non-burst code prefetch cycle, HOLD is acknowledged after
the system asserts RDY#. Once HOLD is asserted, the processor blocks all bus activities until
the system releases the bus (by de-asserting HOLD).