Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 229
Bus Operation—Intel
®
Quark Core
X1000 Core invalidates the line if the system snoop hits an S-state, E-state, or M-state
line, provided INV was driven high during snooping. If INV is driven low during a snoop
cycle, a modified line is written back to memory and remains in the cache as a write-
back line; a write-through line also remains in the cache as a write-through line.
After asserting AHOLD or BOFF#, the external bus master driving the snoop cycle must
wait for two clocks before driving the snoop address and asserting EADS#. If snooping
is done under HOLD, the master performing the snoop must wait for at least one clock
cycle before driving the snoop addresses and asserting EADS#. INV should be driven
low during read operations to minimize invalidations, and INV should be driven high to
invalidate a cache line during write operations. The Write-Back Enhanced Intel
®
Quark
SoC X1000 Core asserts HITM# if the cycle hits a modified line in the cache. This
output signal becomes valid two clock periods after EADS# is valid on the bus. HITM#
remains asserted until the modified line is written back and remains asserted until the
RDY# or BRDY# of the snoop cycle is asserted. Snoop operations could interrupt an
ongoing bus operation in both the Standard Bus and Enhanced Bus modes.
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core can accept EADS# in every
clock period while in Standard Bus mode. In Enhanced Bus mode, the Write-Back
Enhanced Intel
®
Quark SoC X1000 Core can accept EADS# every other clock period or
until a snoop hits an M-state line.
The Write-Back Enhanced Intel
®
Quark SoC X1000 Core does not accept any further
snoop cycles inputs until the previous snoop write-back operation is completed.
All write-back cycles adhere to the burst address sequence of 0-4-8-C. The CACHE#,
PWT, and PCD output pins are asserted and the KEN# and WB/WT# input pins are
ignored. Write-back cycles can be either burst or non-burst. All write-back operations
write 16 bytes of data to memory corresponding to the modified line that hit during the
snoop.
Note: The Write-Back Enhanced Intel
®
Quark SoC X1000 Core accepts BS8# and BS16# line-
fill cycles, but not on replacement or snoop-forced write-back cycles.
10.4.3.1 Snoop Collision with a Current Cache Line Operation
The system can also perform snooping concurrent with a cache access and may collide
with a current cache bus cycle. Table 71 lists some scenarios and the results of a snoop
operation colliding with an on-going cache fill or replacement cycle.