Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
234 Order Number: 329679-001US
3. If the snoop occurs when INV = “1”, the processor never updates the cache with
the fill data.
4. If the snoop occurs when INV = “0”, the processor loads the line into the internal
cache.
10.4.3.3 Snoop During Replacement Write-Back
If the cache contains valid data during a line fill, one of the cache lines may be replaced
as determined by the Least Recently Used (LRU) algorithm. Refer to Chapter 7.0, “On-
Chip Cache” for a detailed discussion of the LRU algorithm. If the line being replaced is
modified, this line is written back to maintain cache coherency. When a replacement
write-back cycle is in progress, it might be necessary to snoop the line that is being
written back (see Figure 116).
Figure 116. Snoop to the Line that is Being Replaced
If the replacement write-back cycle is burst and there is a snoop hit to the same line as
the line that is being replaced, the on-going replacement cycle runs to completion.
HITM# is asserted until the line is written back and the snoop write-back is not
initiated. In this case, the replacement write-back is converted to the snoop write-back,
and HITM# is asserted and de-asserted without a specific ADS# to initiate the write-
back cycle.
242202-153
CLK
AHOLD
EADS#
INV
HITM#
A31–A4
A3–A2
ADS#
1234567891011
W/R#
To Processor
BRDY#
CACHE#
BLAST#
0 8 C
Replace
048C
Replace
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