Specifications

Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
238 Order Number: 329679-001US
10.4.3.5.1 Snoop under HOLD during Cache Line Fill
As shown in Figure 119, HOLD (asserted in clock two) does not fracture the burst cache
line-fill cycle until the line fill is completed (in clock five). Upon completing the line fill in
clock five, the Write-Back Enhanced Intel
®
Quark SoC X1000 Core asserts HLDA and
the system begins snooping by driving EADS# and INV in the following clock period.
The assertion of HITM# in clock nine indicates that the snoop cycle has hit a modified
line and the cache line is written back to memory. The assertion of HITM# in clock nine
and CACHE# and ADS# in clock 11 identifies the beginning of the snoop write-back
cycle. The snoop write-back cycle begins upon the de-assertion of HOLD, and HITM# is
asserted throughout the duration of the snoop write-back cycle.
Figure 119. Snoop under HOLD during Line Fill
If HOLD is asserted during a non-cacheable, non-burst code prefetch cycle, as shown in
Figure 120, the Write-Back Enhanced Intel
®
Quark SoC X1000 Core issues HLDA in
clock seven (which is the clock period in which the next RDY# is asserted). If the
system snoop hits a modified line, the snoop write-back cycle begins after HOLD is
released. After the snoop write-back cycle is completed, an ADS# is issued and the
code prefetch cycle resumes.
242202-156
CLK
HOLD
HLDA
INV
HITM#
A31–A4
A3–A2
ADS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BLAST#
CACHE#
BRDY#
To Processor
W/R#
0 4 8 C
EADS#
0 4 8 C
Linefill
†
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