Specifications

Intel
®
Quark Core—Architectural Overview
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
24 Order Number: 329679-001US
Figure 2. Address Translation
3.3.2 Segment Register Usage
The main data structure used to organize memory is the segment. On the Intel
®
Quark
SoC X1000 Core, segments are variable sized blocks of linear addresses which have
certain attributes associated with them. There are two main types of segments: code
and data. The segments are of variable size and can be as small as 1 byte or as large
as 4 Gbytes (2
32
bytes).
In order to provide compact instruction encoding, and increase Intel
®
Quark SoC
X1000 Core performance, instructions do not need to explicitly specify which segment
register is used. A default segment register is automatically chosen according to the
rules of Table 3. In general, data references use the selector contained in the DS
register; stack references use the SS register and Instruction fetches use the CS
register. The contents of the Instruction Pointer provide the offset. Special segment
override prefixes allow the explicit use of a given segment register, and override the
implicit rules listed in Table 3. The override prefixes also allow the use of the ES, FS and
GS segment registers.
There are no restrictions regarding the overlapping of the base addresses of any
segments. Thus, all 6 segments could have the base address set to zero and create a
system with a 4-Gbyte linear address space. This creates a system where the virtual
address space is the same as the linear address space. Further details of segmentation
are discussed in Chapter 6.0, “Protected Mode Architecture.”
A5158-01
Effective
Address
32
Physical
Address
32
32
Segmentation
Unit
Selector
R
P
L
Logical or
Virtual Address
13
Descriptor Index
03215
Segment Register
Linear
Address
Paging Unit
(optional use)
Physical
Memory
BE3#–BE0#
A31–A2
031
Effective Address Calculation
Displacement
Index
Base
Scale
1, 2, 3, 4
X
+