Specifications
Intel
®
Quark Core—Bus Operation
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
240 Order Number: 329679-001US
to the system that the processor is performing this sequence of cycles, and that the
processor should be allowed atomic access for the location accessed during the first
locked cycle.
A locked operation is a combination of one or more read cycles followed by one or more
write cycles with the LOCK# pin asserted. Before a locked read cycle is run, the
processor first determines if the corresponding line is in the cache. If the line is present
in the cache, and is in an E or S state, it is invalidated. If the line is in the M state, the
processor does a write-back and then invalidates the line. A locked cycle to an M, S, or
E state line is always forced out to the bus. If the operand is misaligned across cache
lines, the processor could potentially run two write back cycles before starting the first
locked read. In this case the sequence of bus cycles is: write back, write back, locked
read, locked read, locked write and the final locked write. Note that although a total of
six cycles are generated, the LOCK# pin is asserted only during the last four cycles, as
shown in Figure 121.
LOCK# is not deasserted if AHOLD is asserted in the middle of a locked cycle. LOCK#
remains asserted even if there is a snoop write-back during a locked cycle. LOCK# is
floated if BOFF# is asserted in the middle of a locked cycle. However, it is driven LOW
again when the cycle restarts after BOFF#. Locked read cycles are never transformed
into line fills, even if KEN# is asserted. If there are back-to-back locked cycles, the
Write-Back Enhanced Intel
®
Quark SoC X1000 Core does not insert a dead clock
between these two cycles. HOLD is recognized if there are two back-to-back locked
cycles, and LOCK# floats when HLDA is asserted.
Figure 121. Locked Cycles (Back-to-Back)
242202-158
CLK
ADS#
DATA
Ti T1 T2 T1 T2 T1 T2 T1 T2 T1
To Processor
From Processor
RDY#
BRDY#
ADDR
CACHE#
LOCK#
W/R#
Rd1 Wt1 Rd2 Wt2
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