Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 243
Bus Operation—Intel
®
Quark Core
Figure 124. Snoop under AHOLD Overlaying Pseudo-Locked Cycle
10.4.6.2 Snoop under HOLD during Pseudo-Locked Cycles
As shown in Figure 125, HOLD does not fracture the 64-bit burst transfer. The Write-
Back Enhanced Intel
®
Quark SoC X1000 Core does not issue HLDA until clock four.
After the 64-bit transfer is completed, the Write-Back Enhanced Intel
®
Quark SoC
X1000 Core writes back the modified line to memory (if snoop hits a modified line). If
the 64-bit transfer is non-burst, the Write-Back Enhanced Intel
®
Quark SoC X1000
Core can issue HLDA in between bus cycles for a 64-bit transfer.
242202-161
CLK
AHOLD
EADS#
HITM#
A31–A4
A3–A2
ADS#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BLAST#
CACHE#
To Processor
†
W/R#
0 4 8 C
INV
PLOCK#
BRDY#
Write Back Cycle
†