Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 247
Debugging Support—Intel
®
Quark Core
11.3.1 Linear Address Breakpoint Registers (DR[3:0])
Up to four breakpoint addresses can be specified by writing to Debug Registers
DR[3:0], shown in Figure 72. The breakpoint addresses specified are 32-bit linear
addresses. Intel
®
Quark SoC X1000 Core hardware continuously compares the linear
breakpoint addresses in DR[3:0] with the linear addresses generated by executing
software (a linear address is the result of computing the effective address and adding
the 32-bit segment base address). Note that when paging is not enabled, the linear
address equals the physical address. If paging is enabled, the linear address is
translated to a physical 32-bit address by the on-chip paging unit. Regardless of
whether paging is enabled or not, however, the breakpoint registers hold linear
addresses.
11.3.2 Debug Control Register (DR7)
A Debug Control Register, DR7 shown in Figure 72, allows several debug control
functions, such as enabling the breakpoints and setting up other control options for the
breakpoints. The fields within the Debug Control Register, DR7, are as follows:
LENi (breakpoint length specification bits)
A 2-bit LEN field exists for each of the four breakpoints. LEN specifies the length of the
associated breakpoint field. The choices for data breakpoints are: 1 byte, 2 bytes, and
4 bytes. Instruction execution breakpoints must have a length of 1 (LENi = 00).
Encoding of the LENi field is as described in Table 73.
The LENi field controls the size of breakpoint field i by controlling whether all low-order
linear address bits in the breakpoint address register are used to detect the breakpoint
event. Therefore, all breakpoint fields are aligned: 2-byte breakpoint fields begin on
word boundaries, and 4-byte breakpoint fields begin on dword boundaries.
Figure 127 is an example of various size breakpoint fields. Assume the breakpoint
linear address in DR2 is 00000005H. In that situation, Figure 127 indicates the region
of the breakpoint field for lengths of 1, 2, or 4 bytes.
Table 72. Debug Registers
31 16 15 0
Breakpoint 0 Linear Address DR0
Breakpoint 1 Linear Address DR1
Breakpoint 2 Linear Address DR2
Breakpoint 3 Linear Address DR3
Intel Reserved. Do not define. DR4
Intel Reserved. Do not define. DR5
0
B
T
B
S
B
D
000000000
B
3
B
2
B
1
B
0
DR6
LEN
3
R
3
W
3
LEN
2
R
2
W
2
LEN
1
R
1
W
1
LEN
0
R
0
W
0
00
G
D
000
G
E
L
E
G
3
L
3
G
2
L
2
G
1
L
1
G
0
L
0
DR7
31 16 15 0
Note: 0 indicates Intel reserved: Do not define.