Specifications

Intel
®
Quark Core—Debugging Support
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
250 Order Number: 329679-001US
Gi and Li (breakpoint enable, global and local)
When either Gi or Li is set, then the associated breakpoint (as defined by the linear
address in DRi, the length in LENi and the usage criteria in RWi) is enabled. When
either Gi or Li is set, and the Intel
®
Quark SoC X1000 Core detects the ith breakpoint
condition, the exception 1 handler is invoked.
When the Intel
®
Quark SoC X1000 Core performs a task switch to a new Task State
Segment (TSS), all Li bits are cleared. Thus, the Li bits support fast task switching out
of tasks that use some task-local breakpoint registers. The Li bits are cleared by the
Intel
®
Quark SoC X1000 Core during a task switch to avoid spurious exceptions in the
new task. Note that the breakpoints must be re-enabled under software control.
All Intel
®
Quark SoC X1000 Core Gi bits are unaffected during a task switch. The Gi bits
support breakpoints that are active in all tasks executing in the system.
11.3.3 Debug Status Register (DR6)
A Debug Status Register (DR6 shown in Figure 72) allows the exception 1 handler to
easily determine why it was invoked. Note that the exception 1 handler can be invoked
as a result of one of several events:
• DR0 Breakpoint fault/trap
• DR1 Breakpoint fault/trap
• XDR2 Breakpoint fault/trap
• XDR3 Breakpoint fault/trap
• XSingle-step (TF) trap
• XTask switch trap
• XFault due to attempted debug register access when GD=1
The Debug Status Register contains single-bit flags for each of the possible events that
invoke exception 1. Note below that some of these events are faults (exception taken
before the instruction is executed), whereas other events are traps (exception taken
after the debug events occurred).
The flags in DR6 are set by hardware but never cleared by hardware. Exception 1
handler software should clear DR6 before returning to the user program to avoid future
confusion in identifying the source of exception 1.
The fields within the Debug Status Register, DR6, are as follows:
Bi (debug fault/trap due to breakpoint 0–3)
Four breakpoint indicator flags, B[3:0], correspond one-to-one with the breakpoint
registers in DR[3:0]. A flag Bi is set when the condition described by DRi, LENi, and
RWi occurs.
If Gi or Li is set, and if the ith breakpoint is detected, the Intel
®
Quark SoC X1000 Core
invokes the exception 1 handler. The exception is handled as a fault when an
instruction execution breakpoint occurs, or as a trap if a data breakpoint occurs.
Note: A flag Bi is set whenever the hardware detects a match condition on enabled breakpoint
i. When a match is detected on at least one enabled breakpoint i, the hardware
immediately sets all Bi bits that correspond to breakpoint conditions matching at that
instant, whether enabled or not. Although the exception 1 handler may see that
multiple Bi bits are set, only those set Bi bits that correspond to enabled breakpoints (Li
or Gi set) are true indications of why the exception 1 handler was invoked.