Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
252 Order Number: 329679-001US
12.0 Instruction Set Summary
This chapter describes the entire encoding structure and provides definitions of all
fields occurring within the Intel
®
Quark SoC X1000 Core instructions.
Section 12.2.5, “Intel
®
Quark SoC X1000 Core Instructions” on page 263 provides
product-specific details.
• Detailed information on the CPUID instructions can be found in Appendix C,
“Feature Determination.”
12.1 Instruction Set
The Intel
®
Quark SoC X1000 Core instruction set can be divided into the following
categories of operations:
• Data Transfer
• Arithmetic
•Shift/Rotate
• String Manipulation
• Bit Manipulation
• Control Transfer
• High Level Language Support
• Operating System Support
• Processor Control
All Intel
®
Quark SoC X1000 Core instructions operate on either 0, 1, 2 or 3 operands;
where an operand resides in a register, in the instruction itself, or in memory. Most
zero-operand instructions (e.g., CLI, STI) take only one byte. One-operand instructions
generally are two bytes long. The average instruction is 3.2-bytes long. Because the
Intel
®
Quark SoC X1000 Core has a 32-byte instruction queue, an average of 10
instructions are prefetched. The use of two operands permits the following types of
common instructions:
• Register to register
•Memory to register
•Memory to memory
• Immediate to register
• Register to memory
• Immediate to memory
The operands can be 8-, 16-, or 32-bits long. As a general rule, when executing 32-bit
code, operands are 8 or 32 bits; when executing 16-bit code, operands are 8 or 16
bits. Prefixes can be added to all instructions to override the default length of the
operands (i.e., to use 32-bit operands for 16-bit code, or 16-bit operands for 32-bit
code).