Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 259
Instruction Set Summary—Intel
®
Quark Core
Table 82. Encoding of 32-Bit Address Mode with “mod r/m” Byte
(No “s-i-b” Byte Present)
mod r/m Effective Address mod r/m Effective Address
00 000 DS:[EAX] 10 000 DS:[EAX+d32]
00 001 DS:[ECX] 10 001 DS:[ECX+d32]
00 010 DS:[EDX] 10 010 DS:[EDX+d32]
00 011 DS:[EBX] 10 011 DS:[EBX+d32]
00 100 s-i-b is present 10 100 s-i-b is present
00 101 DS:d32 10 101 SS:[EBP+d32]
00 110 DS:[ESI] 10 110 DS:[ESI+d32]
00 111 DS:[EDI] 10 111 DS:[EDI+d32]
01 000 DS:[EAX+d8] 11 000 register–see below
01 001 DS:[ECX+d8] 11 001 register–see below
01 010 DS:[EDX+d8] 11 010 register–see below
01 011 DS:[EBX+d8] 11 011 register–see below
01 100 s-i-b is present 11 100 register–see below
01 101 SS:[EBP+d8] 11 101 register–see below
01 110 DS:[ESI+d8] 11 110 register–see below
01 111 DS:[EDI+d8] 11 111 register–see below
Register Specified by reg or r/m
during 16-Bit Data Operations:
Register Specified by reg or r/m
during 32-Bit Data Operations:
mod r/m
Function of w field
mod r/m
Function of w field
(when w=0) (when w=1) (when w=0) (when w=1)
11 000 AL AX 11 000 AL EAX
11 001 CL CX 11 001 CL ECX
11 010 DL DX 11 010 DL EDX
11 011 BL BX 11 011 BL EBX
11 100 AH SP 11 100 AH ESP
11 101 CH BP 11 101 CH EBP
11 110 DH SI 11 110 DH ESI
11 111 BH DI 11 111 BH EDI