Specifications

Intel
®
Quark Core—Architectural Overview
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
26 Order Number: 329679-001US
3.5.2 Register and Immediate Modes
The following two addressing modes provide for instructions that operate on register or
immediate operands:
• Register Operand Mode: The operand is located in one of the 8-, 16- or 32-bit
general registers.
• Immediate Operand Mode: The operand is included in the instruction as part of the
opcode.
3.5.3 32-Bit Memory Addressing Modes
The remaining modes provide a mechanism for specifying the effective address of an
operand. The linear address consists of two components: the segment base address
and an effective address. The effective address is calculated by using combinations of
the following four address elements:
• DISPLACEMENT: An 8-, or 32-bit immediate value, following the instruction.
• BASE: The contents of any general purpose register. The base registers are
generally used by compilers to point to the start of the local variable area.
• INDEX: The contents of any general purpose register except for ESP. The index
registers are used to access the elements of an array, or a string of characters.
• SCALE: The index register's value can be multiplied by a scale factor, either 1, 2, 4
or 8. Scaled index mode is especially useful for accessing arrays or structures.
Combinations of these 4 components make up the 9 additional addressing modes.
There is no performance penalty for using any of these addressing combinations,
because the effective address calculation is pipelined with the execution of other
instructions. The one exception is the simultaneous use of Base and Index components,
which requires one additional clock.
As shown in Figure 3, the effective address (EA) of an operand is calculated according
to the following formula:
EA = Base Reg + (Index Reg * Scaling) + Displacement
Direct Mode: The operand’s offset is contained as part of the instruction as an 8-, 16-
or 32-bit displacement.
Example: INC Word PTR [500]
Register Indirect Mode: A BASE register contains the address of the operand.
Example: MOV [ECX], EDX
Based Mode: A BASE register's contents is added to a DISPLACEMENT to form the
operand's offset.
Example: MOV ECX, [EAX+24]
Index Mode: An INDEX register’s contents is added to a DISPLACEMENT to form the
operand's offset.
Example: ADD EAX, TABLE[ESI]
Scaled Index Mode: An INDEX register's contents is multiplied by a scaling factor
which is added to a DISPLACEMENT to form the operand's offset.
Example: IMUL EBX, TABLE[ESI*4],7
Based Index Mode: The contents of a BASE register is added to the contents of an
INDEX register to form the effective address of an operand.
Example: MOV EAX, [ESI] [EBX]