Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
260 Order Number: 329679-001US
12.2.3.5 Encoding of Operation Direction (d) Field
In many two-operand instructions the d field is present to indicate which operand is
considered the source and which is the destination.
Table 83. Encoding of 32-Bit Address Mode (“mod r/m” Byte and “s-i-b” Byte Present)
mod base Effective Address ss Scale Factor
00 000 DS:[EAX+(scaled index)] 00 x1
00 001 DS:[ECX+(scaled index)] 01 x2
00 010 DS:[EDX+(scaled index)] 10 x4
00 011 DS:[EBX+(scaled index)] 11 x8
00 100 SS:[ESP+(scaled index)] Index Index Register
00 101 DS:[d32+(scaled index)] 000 EAX
00 110 DS:[ESI+(scaled index)] 001 ECX
00 111 DS:[EDI+(scaled index)] 010 EDX
01 000 DS:[EAX+(scaled index)+d8] 011 EBX
01 001 DS:[ECX+(scaled index)+d8] 100 no index reg†
01 010 DS:[EDX+(scaled index)+d8] 101 EBP
01 011 DS:[EBX+(scaled index)+d8] 110 ESI
01 100 SS:[ESP+(scaled index)+d8] 111 EDI
01 101 SS:[EBP+(scaled index)+d8]
Note: When index field is 100, indicating “no index
register,” then ss field MUST equal 00. When
index is 100 and ss does not equal 00, the
effective address is undefined.
01 110 DS:[ESI+(scaled index)+d8]
01 111 DS:[EDI+(scaled index)+d8]
10 000 DS:[EAX+(scaled index)+d32]
10 001 DS:[ECX+(scaled index)+d32]
10 010 DS:[EDX+(scaled index)+d32]
10 011 DS:[EBX+(scaled index)+d32]
10 100 SS:[ESP+(scaled index)+d32]
10 101 SS:[EBP+(scaled index)+d32]
10 110 DS:[ESI+(scaled index)+d32]
10 111 DS:[EDI+(scaled index)+d32]
Note: Mod field in “mod r/m” byte; ss, index,
base fields in “s-i-b” byte.
Table 84. Encoding of Operation Direction (d) Field
d Direction of Operation
0
Register/Memory ← Register “reg” Field Indicates Source Operand; “mod r/m” or
“mod ss index base” Indicates Destination Operand
1
Register ← Register/Memory “reg” Field Indicates Destination Operand; “mod
r/m” or “mod ss index base” Indicates Source Operand