Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
262 Order Number: 329679-001US
12.2.4 Encoding of Floating-Point Instruction Fields
Instructions for the FPU assume one of the five forms shown in Table 88. In all cases,
instructions are at least two bytes long and begin with the bit pattern 11011B.
The mod (Mode field) and r/m (Register/Memory specifier) have the same
interpretation as the corresponding fields of the integer instructions.
The s-i-b (Scale Index Base) byte and disp (displacement) are optionally present in
instructions that have mod and r/m fields. Their presence depends on the values of
mod and r/m, as for integer instructions.
Table 87. Encoding of Control or Debug or Test Register (eee) Field
eee Code TTReg Name
When Interpreted as Control Register Field:
000 CR0
010 CR2
011 CR3
When Interpreted as Debug Register Field:
000 DR0
001 DR1
010 DR2
011 DR3
110 DR6
111 DR7
When Interpreted as Test Register Field:
011 TR3
100 TR4
101 TR5
110 TR6
111 TR7
Note: Do not use any other encoding