Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 265
Instruction Set Summary—Intel
®
Quark Core
This instruction must be executed at privilege level 0 or in real-address mode;
otherwise, a general protection exception #GP(0) is generated. Specifying a reserved
or unimplemented MSR address in ECX will also cause a general protection exception.
The processor will also generate a general protection exception if software attempts to
write to bits in a reserved MSR.
MSRs control functions for testability, execution tracing, performance-monitoring and
machine check errors. Note that each processor family has its own set of MSRs.
The WRMSR instruction is a serializing instruction.
The CPUID instruction should be used to determine whether MSRs are supported
(CPUID.01H:EDX[5] = 1) before using this instruction.
12.3 Clock Count Summary
To calculate elapsed time for an instruction, multiply the instruction clock count, as
listed in Table 89 through Table 93, by the processor core clock period.
12.3.1 Instruction Clock Count Assumptions
The Intel
®
Quark SoC X1000 Core instruction core clock count tables give clock counts
assuming data and instruction accesses hit in the cache. The combined instruction and
data cache hit rate is greater than 90%.
A cache miss forces the Intel
®
Quark SoC X1000 Core to run an external bus cycle. The
32-bit burst bus is defined as r-b-w, where:
r = The number of bus clocks in the first cycle of a burst read or the
number of clocks per data cycle in a non-burst read.
b = The number of bus clocks for the second and subsequent cycles
in a burst read.
w = The number of bus clocks for a write.
The clock counts in the cache miss penalty column assume a 2-1-2 bus. For slower
buses add r-2 clocks to the cache miss penalty for the first dword accessed. Other
factors also affect instruction clock counts.
Instruction Clock Count Assumptions
1. The external bus is available for reads or writes at all times; otherwise, add bus
clocks to reads until the bus is available.
2. Accesses are aligned. Add three core clocks to each misaligned access.
3. Cache fills complete before subsequent accesses to the same line. When a read
misses the cache during a cache fill due to a previous read or pre-fetch, the read
must wait for the cache fill to complete. When a read or write accesses a cache line
still being filled, it must wait for the fill to complete.
4. When an effective address is calculated, the base register is not the destination
register of the preceding instruction. When the base register is the destination
register of the preceding instruction, add 1 to the core clock counts shown. Back-
to-back PUSH and POP instructions are not affected by this rule.
5. An effective address calculation uses one base register and does not use an index
register. However, when the effective address calculation uses an index register,
one core clock may be added to the clock count shown.
6. The target of a jump is in the cache. If not, add r clocks for accessing the
destination instruction of a jump. When the destination instruction is not
completely contained in the first dword read, add a maximum of 3b bus clocks.