Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
266 Order Number: 329679-001US
When the destination instruction is not completely contained in the first 16 byte
burst, add a maximum of r+3b bus clocks.
7. If no write buffer delay occurs, w bus clocks are added only when all write buffers
are full.
8. Displacement and immediate must not be used together. If displacement and
immediate are used together, one core clock may be added to the core clock count
shown.
9. No invalidate cycles. Add a delay of one bus clock for each invalidate cycle if the
invalidate cycle contends for the internal cache/external bus when the Intel
®
Quark
SoC X1000 Core needs to use it.
10.Page translation hits in TLB. A TLB miss adds 13, 21 or 28 bus clocks + 1 possible
core clock to the instruction depending on whether the Accessed and/or Dirty bit in
neither, one, or both of the page entries must be set in memory. This assumes that
neither page entry is in the data cache and a page fault does not occur on the
address translation.
11.No exceptions are detected during instruction execution. Refer to Table 91 for extra
clocks when an interrupt is detected.
12.Instructions that read multiple consecutive data items (i.e., task switch, POPA,
etc.) and miss the cache are assumed to start the first access on a 16-byte
boundary. If not, an extra cache line fill may be necessary, which may add up to
(r+3b) bus clocks to the cache miss penalty.