Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
268 Order Number: 329679-001US
LEA = Load EA to Register 1000 1101 : mod reg r/m
no index register 1
with index register 2
Instruction
ADD = Add
ADC = Add with Carry
AND = Logical AND
OR = Logical OR
SUB = Subtract
SBB = Subtract with Borrow
XOR = Logical Exclusive OR
TTT
000
010
100
001
101
011
110
reg1 to reg2 00TT T00w : 11 reg1 reg2 1
reg2 to reg1 00TT T01w : 11 reg1 reg2 1
memory to register 00TT T01w : mod reg r/m 2 2
register to memory 00TT T00w : mod reg r/m 3 6/2 U/L
immediate to register
1000 00sw : 11 TTT reg : immediate
register
1
immediate to
Accumulator
00TT T10w : immediate data 1
immediate to memory
1000 00sw : mod TTT r/m : immediate
data
36/2U/L
Instruction
INC = Increment
DEC = Decrement
TTT
000
001
reg 1111 111w : 11 TTT reg 1
or 01TTT reg 1
memory 1111 111w : mod TTT r/m 3 6/2 U/L
Instruction
NOT = Logical Complement
NEG = Negate
TTT
010
011
reg 1111 011w : 11 TTT reg 1
memory 1111 011w : mod TTT r/m 3 6/2 U/L
CMP = Compare
reg1 with reg2 0011 100w : 11 reg1 reg2 1
reg2 with reg1 0011 101w : 11 reg1 reg2 1
memory with register 0011 100w : mod reg r/m 2 2
register with memory 0011 101w : mod reg r/m 2 2
immediate with register 1000 00sw : 11 111 reg : immediate data 1
immediate with acc. 0011 110w : immediate data 1
immediate with memory
1000 00sw : mod 111 r/m : immediate
data
22
Table 89. Clock Count Summary (Sheet 2 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.