Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
270 Order Number: 329679-001US
IMUL = Integer Multiply (signed)
acc. with register 1111 011w : 11 101 reg
Multiplier-Byte
Word
Dword
5/5
5/6
6/12
MN/MX,3
MN/MX,3
MN/MX,3
acc. with memory 1111 011w : mod 1 01 r/m
Multiplier-Byte
Word
Dword
5/5
5/6
6/12
MN/MX,3
MN/MX,3
MN/MX,3
reg1 with reg2 0000 1111 : 1010 1111 : 11 reg1 reg2
Multiplier-Byte
Word
Dword
5/5
5/6
6/12
MN/MX,3
MN/MX,3
MN/MX,3
register with memory 0000 1111 : 1010 1111 : mod reg r/m
Multiplier-Byte
Word
Dword
5/5
5/6
6/12
MN/MX,3
MN/MX,3
MN/MX,3
reg1 with imm. to reg2
0110 10s1 : 11 reg1 reg2 : immediate
data
Multiplier-Byte
Word
Dword
5/5
5/6
6/12
MN/MX,3
MN/MX,3
MN/MX,3
mem. with imm. to reg.
0110 10s1 : mod reg r/m : immediate
data
Multiplier-Byte
Word
Dword
5/5
5/6
6/12
MN/MX,3
MN/MX,3
MN/MX,3
DIV = Divide (unsigned)
acc. by register 1111 011w : 1111 0 reg
Divisor-Byte
Word
Dword
16
24
40
acc. by memory 1111 011w : mod 11 0 r/m
Divisor-Byte
Word
Dword
16
24
40
IDIV = Integer Divide
(signed)
acc. by register 1111 011w : 1111 1 reg
Divisor-Byte
Word
Dword
19
27
43
acc. by memory 1111 011w : mod 11 1 r/m
Divisor-Byte
Word
Dword
20
28
44
CBW = Convert Byte to
Word
1001 1000 3
Table 89. Clock Count Summary (Sheet 4 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.