Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
274 Order Number: 329679-001US
RET = Return from CALL
intersegment 1100 1010 13 8 R,7
to same level
to outet lever
17
35
9
12
P,9
P,9
intersegment adding
imm. to SP
1100 1010 : 16-bit disp. 14 8 R,7
to same level
to outer level
18
36
9
12
P,9
P,9
JMP = Unconditional Jump
Direct intersegment 1110 1010 : unsigned full offset, selector 17 2 R,7,22
to same level
thru Call Gate to same level
thru TSS
thru Task Gate
19
32
42+TS
43+TS
3
6
3
3
P,9
P,9
P,10,9
P,10,9,
Indirect intersegment 1111 1111 : mod 011 r/m 13 9 R,7,9
to same level
thru Call Gate to same level
thru TSS
thru Task Gate
18
31
41+TS
42+TS
10
13
10
10
P,9
P,9
P,10,9
P,10,9,
BIT MANIPULATION
BT = Test Bit
register, immediate
0000 1111 : 1011 1010 : 11 100 reg :
imm. 8-bit data
3
memory, immediate
0000 1111 : 1011 1010 : mod 100 r/m :
imm. 8-bit data
31
reg1, reg2 0000 1111 : 1010 0011 : 11 reg2 reg1 3
memory, reg 0000 1111 : 1010 0011 : mod reg r/m 8 2
Instruction
BTS = Test Bit and Set
BTR = Test Bit and Reset
BTC = Test Bit and
Complement
TTT
101
110
111
register, immediate
0000 1111 : 1011 1010 : 11 TTT reg
imm. 8-bit data
6
memory, immediate
0000 1111 : 1011 1010 : mod TTT r/m
imm. 8-bit data
8U/L
reg1, reg2 0000 1111 : 10TT T011 : 1 1 reg2 reg1 6
memory, reg 0000 1111 : 10TT T011 : mod reg r/m 13 U/L
BSF = Scan Bit Forward
reg1, reg2 0000 1111 : 1011 1100 : 11 reg2 reg1 6/42
MN/MX,
12
memory, reg 0000 1111 : 1011 1100 : mod reg r/m 7/43 2 MN/MX, 15
BSR = Scan Bit Reverse
reg1, reg2 0000 1111 : 1011 1101 : 11 reg2 reg1 6/103 MN/MX, 14
memory, reg 0000 1111 : 1011 1101 : mod reg r/m 7/104 1 MN/MX, 15
Table 89. Clock Count Summary (Sheet 8 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.