Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
278 Order Number: 329679-001US
LTR = Load Task Register
From register 0000 1111 : 0000 0000 : 11 011 reg 20
From memory 0000 1111 : 0000 0000 : mod 011 r/m 20
SGDT = Store Global Descriptor Table
0000 1111 : 0000 0001 : mod 000 r/m 10
SIDT = Store Interrupt Descriptor Table
0000 1111 : 0000 0001 : mod 001 r/m 2
SLDT = Store Local Descriptor Table
To register 0000 1111 : 0000 0000 : 11 000 reg 2
To memory 0000 1111 : 0000 0001 : mod 000 r/m 3
SMSW = Store Machine Status Word
To register 0000 1111 : 0000 0001 : 11 000 reg 2
To memory 0000 1111 : 0000 0001 : mod 100 r/m 3
STR = Store Task Register
To register 0000 1111 : 0000 0000 : 11 001 r/m 2
To memory 0000 1111 : 0000 0000 : mod 001 r/m 3
VERR = Verify Read Access
Register 0000 1111 : 0000 0000 : 11 100 r/m 11 3
Memory 0000 1111 : 0000 0000 : mod 100 r/m 11 7
VERW = Verify Write Access
To register 0000 1111 : 0000 0000 : 11 101 r/m 11 3
To memory 0000 1111 : 0000 0000 : mod 101 r/m 11 7
INTERRUPT INSTRUCTIONS
INTn = Interrupt Type n 1100 1101 : type INT+4/0 RV/P, 21
INT3 = Interrupt Type 3 1100 1100 INT+0 21
INTO = Interrupt 4 if Overflow Flag Set
1100 1110
Taken
Not Taken
INT+2
3
21
21
BOUND = Interrupt 5 if Detect Value Out Range
0110 0010 : mod reg r/m
If in range
If out of range
7
INT+24
7
7
21
21
IRET = Interrupt Return 1100 1111
Real Mode/Virtual Mode
Protected Mode
To same level
To outer level
To nested task
(EFLAGS.NT=1)
15
20
36
TS+32
8
11
19
4
9
9
9,10
Table 89. Clock Count Summary (Sheet 12 of 13)
Instruction Format
Cache
Hit
Penalty
if
Cache
Miss
Notes
Note: See Table 92 for notes and abbreviations for items in this table.