Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 283
Instruction Set Summary—Intel
®
Quark Core
Table 94. Floating-Point Clock Count Summary (Sheet 1 of 8)
Instruction Format
Cache Hit
Avg (Lower
Range...
Upper
Range)
Penalty
if
Cache
Miss
Concurrent
Execution
Avg (Lower
Range- Upper
Range)
Notes
DATA TRANSFER
FLD = Real Load to ST(0)
32-bit memory 11011 001 : mod 000 r/m : s-i-b/disp. 3 2
64-bit memory 11011 101 : mod 000 r/m : s-i-b/disp. 3 3
80-bit memory 11011 011 : mod 101 r/m : s-i-b/disp. 6 4
ST(i) 11011 001 : 11000 ST(i) 4
FILD = Integer Load to ST(0)
16-bit memory 11011 111 : mod 000 r/m : s-i-b/disp. 14.5(13-16) 2 4
32-bit memory 11011 011 : mod 000 r/m : s-i-b/disp. 11.5(9-12) 2 4(2-4)
64-bit memory 11011 111 : mod 101 r/m : s-i-b/disp. 16.8(10-18) 3 7.8(2-8)
FBLD = BCD Load to ST(0)
11011 111 : mod 100 r/m : s-i-b/disp. 75(70-103) 4 7.7(2-8)
FST = Store Real from ST(0)
32-bit memory 11011 011 : mod 010 r/m : s-i-b/disp. 7 1
64-bit memory 11011 101 : mod 010 r/m : s-i-b/disp. 8 2
ST(i) 11011 101 : 11001 ST(i) 3
FSTP = Store Real from ST(0) and Pop
32-bit memory 11011 011 : mod 011 r/m : s-i-b/disp. 7 1
64-bit memory 11011 101 : mod 011 r/m : s-i-b/disp. 8 2
80-bit memory 11011 011 : mod 111 r/m : s-i-b/disp. 6
ST(i) 11011 101 : 11001 ST(i) 3
FIST = Store Integer from ST(0)
16-bit memory 11011 111 : mod 010 r/m : s-i-b/disp. 33.4(29-34)
32-bit memory 11011 011 : mod 010 r/m : s-i-b/disp. 32.4(28-34)
FISTP = Store Integer from ST(0) and Pop
16-bit memory 11011 111 : mod 011 r/m : s-i-b/disp. 33.4(29-34)
32-bit memory 11011 011 : mod 011 r/m : s-i-b/disp. 33.4(29-34)
64-bit memory 11011 111 : mod 111 r/m : s-i-b/disp. 33.4(29-34)
FBSTP = Store BCD from ST(0) and Pop
11011 111 : mod 110 r/m : s-i-b/disp. 175(172-176)
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).