Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 285
Instruction Set Summary—Intel
®
Quark Core
CONSTANTS
FLDZ = Load +0.0 Into ST(0)
11011 001 : 1110 1110 : 4
FLD1 = Load +1.0 Into ST(0)
11011 001 : 1110 1000 : 4
FLDP1 = Load p Into ST(0)
11011 001 : 1110 1011 : 8 2
FLDL2T = Load log2(10) Into ST(0)
11011 001 : 1110 1001 : 8 2
FLDL2E = Load log2(e) Into ST(0)
11011 001 : 1110 1010 : 8 2
FLDLG2 = Load log10(2) Into ST(0)
11011 001 : 1110 1100 : 8 2
FLDLN2 = Load loge(2) Into ST(0)
11011 001 : 1110 1101 : 8 2
ARITHMETIC
FADD = Add Real with ST(0)
ST(0)←ST(0) + 32-bit memory
11011 000 : mod 000 r/m : s-i-b/disp. 10(8-20) 2 7(5-17)
ST(0)←ST(0) + 64-bit memory
11011 100 : mod 000 r/m : s-i-b/disp. 10(8-20) 3 7(5-17)
ST(d)←ST(0) + ST(i)
11011 d00 : 11000 ST(i) 10(8-20) 7(5-17)
FADDP = Add real with ST(0) and Pop (ST(i)← ST(0)
+ST(i))
11011 110 : 11000 ST(i) : 10(8-20) 7(5-17)
Table 94. Floating-Point Clock Count Summary (Sheet 3 of 8)
Instruction Format
Cache Hit
Avg (Lower
Range...
Upper
Range)
Penalty
if
Cache
Miss
Concurrent
Execution
Avg (Lower
Range- Upper
Range)
Notes
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).