Specifications

Intel
®
Quark Core—Instruction Set Summary
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
286 Order Number: 329679-001US
FSUB = Subtract Real from ST(0)
ST(0)←ST(0) – 32-bit memory
11011 000 : mod 100 r/m : s-i-b/disp. 10(8-20) 2 7(5-17)
ST(0)←ST(0) – 64-bit memory
11011 100 : mod 100 r/m : s-i-b/disp. 10(8-20) 3 7(5-17)
ST(d)←ST(0) – ST(i)
11011 d00 : 11001 ST(i) 10(8-20) 7(5-17)
FSUBP = Subtract real from ST(0) and Pop (ST(i)← ST(0) -
ST(i))
11011 110 : 11001 ST(i) 10(8-20) 7(5-17)
FSUBR = Subtract Real reversed (Subtract ST(0) from Real)
ST(0)←32-bit memory – ST(0)
11011 000 : mod 101 r/m : s-i-b/disp. 10(8-20) 2 7(5-17)
ST(0)←64-bit memory – ST(0)
11011 100 : mod 101 r/m : s-i-b/disp. 10(8-20) 3 7(5-17)
ST(d)←ST(i) – ST(0)
11011 d00 : 11001 ST(i) 10(8-20) 7(5-17)
FSUBRP = Subtract Real reversed and Pop (ST(i)← ST(i) -
ST(0))
11011 110 : 11100 ST(i) 10(8-20) 7(5-17)
FMUL = Multiply Real with ST(0)
ST(0)←ST(0) X 32-bit memory
11011 000 : mod 001 r/m : s-i-b/disp. 11 2 8
ST(0)←ST(0) X 64-bit memory
11011 100 : mod 001 r/m : s-i-b/disp. 14 3 11
ST(d)←ST(0) X ST(i)
11011 d00 : 11001 ST(i) 16 13
FMULP = Multiply ST(0) with ST(i) and Pop (ST(i)← ST(0)
XST(i))
11011 110 : 11001 ST(i) 16 13
Table 94. Floating-Point Clock Count Summary (Sheet 4 of 8)
Instruction Format
Cache Hit
Avg (Lower
Range...
Upper
Range)
Penalty
if
Cache
Miss
Concurrent
Execution
Avg (Lower
Range- Upper
Range)
Notes
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).