Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 287
Instruction Set Summary—Intel
®
Quark Core
FDIV = Divide ST(0) by Real
ST(0)←ST(0)/ 32-bit memory
11011 000 : mod 110 r/m : s-i-b/disp. 73 2 70 3
ST(0)←ST(0)/ 64-bit memory
11011 100 : mod 110 r/m : s-i-b/disp. 73 3 70 3
ST(d)←ST(0)/ ST(i)
11011 d00 : 11111 ST(i) 73 70 3
FDIVP = Divide ST(0) by ST(i) and Pop (ST(i)← ST(0)/
ST(i))
11011 110 : 11111 ST(i) 73 70 3
FDIVR = Divide real reversed (Real/ST(0))
ST(0)← 32-bit memory/ ST(0)
11011 000 : mod 111 r/m : s-i-b/disp. 73 2 70 3
ST(0)← 64-bit memory/ ST(0)
11011 100 : mod 111 r/m : s-i-b/disp. 73 3 70 3
ST(d)← ST(i)/ ST(0)
11011 d00 : 11110 ST(i) 73 70 3
FDIVRP = Divide real reversed and Pop (ST(i)← ST(i)/
ST(0))
11011 110 : 11110 ST(i) 73 70 3
FIADD = Add Integer to ST(0)
ST(0)←ST(0) + 16-bit memory
11011 110 : mod 000 r/m : s-i-b/disp. 24(20-35) 2 7(5-17)
ST(0)←ST(0) + 32-bit memory
11011 010 : mod 000 r/m : s-i-b/disp. 22.5(19-32) 2 7(5-17)
FISUB = Subtract Integer from ST(0)
ST(0)←ST(0) – 16-bit memory
11011 110 : mod 100 r/m : s-i-b/disp. 24(20-35) 2 7(5-17)
ST(0)←ST(0) – 32-bit memory
11011 010 : mod 100 r/m : s-i-b/disp. 22.5(19-32) 2 7(5-17)
Table 94. Floating-Point Clock Count Summary (Sheet 5 of 8)
Instruction Format
Cache Hit
Avg (Lower
Range...
Upper
Range)
Penalty
if
Cache
Miss
Concurrent
Execution
Avg (Lower
Range- Upper
Range)
Notes
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).