Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 289
Instruction Set Summary—Intel
®
Quark Core
FABS = Absolute value of ST(0)
11011 001 : 1110 0001 3
FCHS = Change Sign of ST(0)
11011 001 : 1110 0000 6
TRANSCENDENTAL
FCOS = Cosine of ST(0)
11011 001 : 1111 1111 241(193-279) 2 6,7
FPTAN = Partial Tangent of ST(0)
11011 001 : 1111 0010 244(200-273) 70 6,7
FPATAN = Partial Arctangent
11011 001 : 1111 0011 289(218-303) 5(2-17) 6
FSIN = Sine of ST(0)
11011 001 : 1111 1110 241(193-279) 2 6,7
FSINCOS = Sine and Cosine of ST(0)
11011 001 : 1111 1011 291(243-329) 2 6,7
F2XM1 = 2ST(0)-1
11011 001 : 1111 0000 242(140-279) 2 6
FYL2X = ST(1) x log2(ST(0))
11011 001 : 1111 0001 311(196-329) 13 6
FYL2XP1 = ST(1) x log2(ST(0) + 1.0)
11011 001 : 1111 1001 313(171-326) 13 6
PROCESSOR CONTROL
FINIT = Initialize FPU
11011 001 : 1110 0011 17 4
FSTSW AX = Store status word into AX
11011 111 : 1110 0000 3 5
FSTSW = Store status word into memory
11011 101 : mod 111 r/m : s-i-b/disp. 3 5
FLDCW = Load control word
11011 001 : mod 101 r/m : s-i-b/disp. 4 2
FSTCW = Store control word
11011 001 : mod 111 r/m : s-i-b/disp. 3 5
Table 94. Floating-Point Clock Count Summary (Sheet 7 of 8)
Instruction Format
Cache Hit
Avg (Lower
Range...
Upper
Range)
Penalty
if
Cache
Miss
Concurrent
Execution
Avg (Lower
Range- Upper
Range)
Notes
Notes:
1. If operand is 0 clock counts = 27.
2. If operand is 0 clock counts = 28.
3. If CW.PC indicates 24 bit precision then subtract 38 clocks.
If CW.PC indicates 53 bit precision then subtract 11 clocks.
4. If there is a numeric error pending from a previous instruction, add 17 clocks.
5. If there is a numeric error pending from a previous instruction, add 18 clocks.
6. The INT pin is polled several times while this function is executing to ensure short interrupt latency.
7. If ABS(operand) is greater than π/4 then add n clocks, where n=(operand/(π/4)).