Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 293
Signal Descriptions—Intel
®
Quark Core
SRESET I
The Soft Reset pin duplicates all the functionality of the RESET pin with the following two exceptions:
1. The SMBASE register retains its previous value.
2. When UP# (I) is asserted, SRESET does not have an effect on the host processor.
For soft resets, SRESET should remain active for at least 15 CLK periods. SRESET is active high. SRESET
is asynchronous but must meet setup and hold times t20 and t21 for recognition in any specific clock.
SMI# I
The System Management Interrupt input is used to invoke System Management Mode (SMM). SMI# is
a falling edge triggered signal that forces the processor into SMM at the completion of the current
instruction. SMI# is recognized on an instruction boundary and at each iteration for repeat string
instructions. SMI# does not break LOCKed bus cycles and cannot interrupt a currently executing SMM.
The processor latches the falling edge of one pending SMI# signal while the processor is executing an
existing SMI#. The nested SMI# is not recognized until after the execution of a Resume (RSM)
instruction.
SMIACT# O
The System Management Interrupt Active is an active low output, indicating that the processor is
operating in SMM. It is asserted when the processor begins to execute the SMI# state save sequence and
remains asserted (low) until the processor executes the last state restore cycle out of SMRAM.
STPCLK# I
The Stop Clock Request input signal indicates that a request has been made to turn off the CLK input.
When the processor recognizes a STPCLK#, the processor stops execution on the next instruction
boundary, unless superseded by a higher priority interrupt, empties all internal pipelines and the write
buffers, and generates a Stop Grant acknowledge bus cycle. STPCLK# is active low and is provided with
an internal pull-up resistor.
STPCLK# is an asynchronous signal, but must remain active until the processor issues the Stop Grant bus
cycle. STPCLK# may be deasserted at any time after the processor has issued the Stop Grant bus cycle.
BUS ARBITRATION
BREQ O
The Bus Request signal indicates that the Intel
®
Quark Core has internally generated a bus request.
BREQ is generated whether or not the Intel
®
Quark Core is driving the bus. BREQ is active high and is
never floated.
HOLD I
The Bus Hold request allows another bus master complete control of the processor bus. In response to
HOLD going active, the Intel
®
Quark Core floats most of its output and input/output pins. HLDA is
asserted after completing the current bus cycle, burst cycle or sequence of locked cycles. The Intel
®
Quark Core remains in this state until HOLD is deasserted. HOLD is active high and is not provided with
an internal pull-down resistor. HOLD must satisfy setup and hold times t18 and t19 for proper operation.
HLDA O
Hold Acknowledge goes active in response to a hold request presented on the HOLD pin. HLDA
indicates that the Intel
®
Quark Core has given the bus to another local bus master. HLDA is driven active
in the same clock in which the Intel
®
Quark Core floats its bus. HLDA is driven inactive when leaving bus
hold. HLDA is active high and remains driven during bus hold.
BOFF# I
The Backoff input forces the Intel
®
Quark Core to float its bus in the next clock. The processor floats all
pins normally floated during bus hold but HLDA is not asserted in response to BOFF#. BOFF# has higher
priority than RDY# or BRDY#; when both are asserted in the same clock, BOFF# takes effect. The
processor remains in bus hold until BOFF# is negated. If a bus cycle was in progress when BOFF# was
asserted, the cycle is restarted. BOFF# is active low and must meet setup and hold times t18 and t19 for
proper operation.
CACHE INVALIDATION
AHOLD I
The Address Hold request allows another bus master access to the processor's address bus for a cache
invalidation cycle. The Intel
®
Quark Core stops driving its address bus in the clock following AHOLD going
active. Only the address bus is floated during address hold, the remainder of the bus remains active.
AHOLD is active high and is provided with a small internal pull-down resistor. For proper operation AHOLD
must meet setup and hold times t18 and t19.
EADS# I
This signal indicates that a valid External Address has been driven onto the Intel
®
Quark Core address
pins. This address is used to perform an internal cache invalidation cycle. EADS# is active low and is
provided with an internal pull-up resistor. EADS# must satisfy setup and hold times t12 and t13 for
proper operation.
CACHE CONTROL
KEN# I
The Cache Enable pin is used to determine whether the current cycle is cacheable. When the Intel
®
Quark Core generates a cycle that can be cached and KEN# is active one clock before RDY# or BRDY#
during the first transfer of the cycle, the cycle becomes a cache line fill cycle. Asserting KEN# one clock
before RDY# during the last read in the cache line fill causes the line to be placed in the on-chip cache.
KEN# is active low and is provided with a small internal pull-up resistor. KEN# must satisfy setup and
hold times t14 and t15 for proper operation.
Table 95. Intel
®
Quark SoC X1000 Core Pin Descriptions (Sheet 3 of 5)
Symbol Type Name and Function