Specifications

Intel
®
Quark Core—Testability
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
296 Order Number: 329679-001US
Appendix B Testability
This appendix contains the following subsections:
• Section B.1, “On-Chip Cache Testing” on page 296
• Section B.2, “Translation Lookaside Buffer (TLB) Testing” on page 300
• Section B.3, “Intel
®
Quark SoC X1000 Core JTAG” on page 304
B.1 On-Chip Cache Testing
The on-chip cache testability hooks are designed to be accessible for assembly
language testing of the cache.
The Intel
®
Quark SoC X1000 Core contains a cache fill buffer and a cache read buffer.
For testability writes, data must be written to the cache fill buffer before it can be
written to a location in the cache. Data must be read from a cache location into the
cache read buffer before the processor can access the data. The cache fill and cache
read buffer are both 128 bits wide.
B.1.1 Cache Testing Registers TR3, TR4 and TR5
Figure 129 shows the three cache testing registers: Cache Data Test Register (TR3),
Cache Status Test Register (TR4), and Cache Control Test Register (TR5). External
access to these registers is provided through MOV reg, TREG and MOV TREG, reg
instructions.
Figure 129. Intel
®
Quark SoC X1000 Core Cache Test Registers
Data
31
0
TR3
Cache Data
Test Register
31
Valid
LRU Bits
(used only
during reads)
Valid Bits
(used only
during reads)
Unused
11109876543210
Tag
Unused
TR4
Cache Status
Test Register
TR5
Cache Control
Test Register
Set Select
Entry
Select
Control
1211 4321 0
Unused
12