Specifications

Intel
®
Quark Core—Testability
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
298 Order Number: 329679-001US
to TR3 initiates the write to the cache fill buffer. The cache fill buffer is loaded with 128
bits of data by writing to TR5 and TR3 four times using a different entry select location
each time.
TR4 must be loaded with the tag and valid bit (bit 10 in TR4) before the contents of the
fill buffer are written to a cache location. The Intel
®
Quark SoC X1000 Core has a 20-
bit tag in TR4.
The contents of the cache fill buffer are written to a cache location by writing TR5 with
a control field of 01 along with the set select and entry select fields. The set select and
entry select field indicate the location in the cache to be written. The normal cache LRU
update circuitry updates the internal LRU bits for the selected set.
Note that a cache testability write can only be done when the cache is disabled for
replaces (the CD bit is control register 0 is reset to 1). Care must be taken when
directly writing to entries in the cache. When the entry is set to overlap an area of
memory that is being used in external memory, that cache entry could inadvertently be
used instead of the external memory. This is exactly the type of operation that one
would desire if the cache were to be used as a high speed RAM. Also, a memory
reference (or any external bus cycle) should not occur in between the move to TR4 and
the move to TR5, in order to avoid having the value in TR4 change due to the memory
reference.
B.1.3 Cache Testability Read
A cache testability read is a two step process. First the contents of the cache location
are read into the cache read buffer. Next the data is examined by reading it out of the
read buffer.
Reading the contents of a cache location into the cache read buffer is initiated by
writing TR5 with the control bits set to 10 and the desired set select and two-bit entry
select. The Intel
®
Quark SoC X1000 Core has an eight-bit select field. In response to
the write to TR5, TR4 is loaded with the 21-bit tag field and the single valid bit from the
cache entry read. TR4 is also loaded with the three LRU bits and four valid bits
corresponding to the cache set that was accessed. The cache read buffer is filled with
the 128-bit value which was found in the data array at the specified location.
The contents of the read buffer are examined by performing four reads of TR3. Before
reading TR3 the entry select bits in TR5 must loaded to indicate which of the four 32-bit
words in the read buffer to transfer into TR3 and the control bits in TR5 must be loaded
with 00. The register read of TR3 initiates the transfer of the 32-bit value from the read
buffer to the specified general purpose register.
Note that it is very important that the entire 128-bit quantity from the read buffer and
also the information from TR4 be read before any memory references are allowed to
occur. When memory operations are allowed to happen, the contents of the read buffer
Table 96. Cache Control Bit Encoding and Effect of Control Bits on Entry Select and Set
Select Functionality
Control Bits
Bit 1 Bit 0 Operation Entry Select Bits Function Set Select Bits
00
Enable: Fill Buffer Write
Read Buffer Read
Select 32-bit location in
fill/read buffer
—
0 1 Perform Cache Write Select an entry in set Select a set to write to
1 0 Perform Cache Read Select an entry in set Select a set to read from
1 1 Perform Cache Flush — —