Specifications

Intel
®
Quark Core—Testability
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
300 Order Number: 329679-001US
Figure 130. TR4 Definition for Standard and Enhanced Bus Modes for the Write-Back
Enhanced Intel
®
Quark SoC X1000 Core
Figure 131. TR5 Definition for Standard and Enhanced Bus Modes for the Write-Back
Enhanced Intel
®
Quark SoC X1000 Core
B.2 Translation Lookaside Buffer (TLB) Testing
The Intel
®
Quark SoC X1000 Core TLB testability hooks are designed to be accessible
for assembly language testing of the TLB.
B.2.1 Translation Lookaside Buffer Organization
The Intel
®
Quark SoC X1000 Core TLB is 4-way set associative and has space for 32
entries. The TLB is logically split into three blocks shown in Figure 132.
The data block is physically split into four arrays, each with space for eight entries. An
entry in the data block is 22 bits wide containing a 20-bit physical address and two bits
for the page attributes. The page attributes are the PCD (page cache disable) bit and
the PWT (page write-through) bit. Refer to Section 7.6 for a discussion of the PCD and
PWT bits.
The tag block is also split into four arrays, one for each of the data arrays. A tag entry
is 21 bits wide containing a 17-bit linear address and four protection bits. The
protection bits are valid (V), user/supervisor (U/S), read/write (R/W) and dirty (D).
The third block contains eight three bit quantities used in the pseudo least recently
used (LRU) replacement algorithm. These bits are called the LRU bits. Unlike the on-
chip cache, the TLB replaces a valid line even when there is an invalid line in a set.
313029282726252423222120191817161514131211109876543210
Standard
Mode
TR4
V
LRU
VALID
(SET)
r
Enhanced
Mode
TR4
r
LRU
V
TAG
TAG
r
H
V
L
Bus
Bus
r
r
313029282726252423222120191817161514131211109876543210
Standard
Mode
TR5
Enhanced
Mode
TR5
S
Set Addr
reserved
reserved
L
F
r
Set Addr
ENT
CTL
Bus
ENT
CTL
Bus