Specifications

Intel
®
Quark Core—Testability
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
302 Order Number: 329679-001US
Figure 133. TLB Test Registers
The seven TLB tag protection bits are described below.
V: The valid bit for this TLB entry
D,D#: The dirty bit for/from the TLB entry
U,U#: The user/supervisor bit for/from the TLB entry
W,W#: The read/write bit for/from the TLB entry
Two bits are used to represent the D, U/S and R/W bits in the TLB tag to permit the
option of a forced miss or hit during a TLB lookup operation. The forced miss or hit
occurs regardless of the state of the actual bit in the TLB. The meaning of these pairs of
bits is given in Table 98.
The operation bit in TR6 determines whether the TLB test operation is a write or a
lookup. The function of the operation bit is given in Table 99.
31
Unused
11109876543210
Linear Address
TR6
TLB Command
Test Register
12
VDD# U
Option
31
Unused
11109876543210
Physical Address
TR7
TLB Data
Test Register
12
PCD
PWT
L2
L1
L0
Unused
Replacement Pointer Select (Writes)
Hit Indication (Lookup)
Replacement Pointer (Writes)
Hit Location (Lookup)
Table 98. Meaning of a Pair of TR6 Protection Bits
TR6 Protection Bit
(B)
TR6 Protection Bit#
(B#)
Meaning on
TLB Write Operation
Meaning on
TLB Lookup Operation
0 0 Undefined Miss any TLB TAG Bit B
0 1 Write 0 to TLB TAG Bit B Match TLB TAG Bit B if 0
1 0 Write 1 to TLB TAG Bit B Match TLB TAG Bit B if 1
1 1 Undefined Match any TLB TAG Bit B
Table 99. TR6 Operation Bit Encoding
TR6 Bit 0 TLB Operation to Be Performed
0TLB Write
1 TLB Lookup