Specifications

Intel
®
Quark Core—Testability
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
308 Order Number: 329679-001US
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
The controller remains in this state as long as TMS is low. When TMS goes high and a
rising edge is applied to TCK, the controller moves to the Exit2-IR state.
B.3.1.15 Exit2-IR State
This is a temporary state. While in this state, if TMS is held high, a rising edge applied
to TCK causes the controller to enter the Update-IR state, which terminates the
scanning process. If TMS is held low and a rising edge is applied to TCK, the controller
enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value
during this state. The instruction does not change in this state.
B.3.1.16 Update-IR State
The instruction shifted into the instruction register is latched onto the parallel output
from the shift-register path on the falling edge of TCK. Once the new instruction has
been latched, it becomes the current instruction.
Test data registers selected by the new current instruction retain the previous value.
B.3.2 TAP Controller Initialization
The TAP controller is automatically initialized when a device is powered up. In addition,
the TAP controller can be initialized by applying a high signal level on the TMS input for
five TCK periods.