Specifications

Intel

Quark Core—Architectural Overview

Intel

Quark SoC X1000 Core

Developer’s Manual October 2013

38 Order Number: 329679-001US

3.7.8 Double Fault

A Double Fault (exception 8) results when the Intel

Quark SoC X1000 Core attempts

to invoke an exception service routine for the segment exceptions (10, 11, 12 or 13),

but in the process of doing so, detects an exception other than a Page Fault (exception

14).

A Double Fault (exception 8) will also be generated when the Intel

Quark SoC X1000

Core attempts to invoke the Page Fault (exception 14) service routine, and detects an

exception other than a second Page Fault. In any functional system, the entire Page

Fault service routine must remain “present” in memory.

When a Double Fault occurs, the Intel

Quark SoC X1000 Core invokes the exception

service routine for exception 8.

3.7.9 Floating-Point Interrupt Vectors

Several interrupt vectors of the Intel

Quark SoC X1000 Core are used to report

exceptional conditions while executing numeric programs in either real or protected

mode. Table 8 shows these interrupts and their causes.

Table 8. Interrupt Vectors Used by FPU

Interrupt Number Cause of Interrupt

A Floating-Point instruction was encountered when EM or TS of the Intel

Quark

SoC X1000 Core control register zero (CR0) was set. EM = 1 indicates that

software emulation of the instruction is required. When TS is set, either a Floating-

Point or WAIT instruction causes interrupt 7. This indicates that the current FPU

context may not belong to the current task.

The first word or doubleword of a numeric operand is not entirely within the limit

of its segment. The return address pushed onto the stack of the exception handler

points at the Floating-Point instruction that caused the exception, including any

prefixes. The FPU has not executed this instruction; the instruction pointer and

data pointer register refer to a previous, correctly executed instruction.

The previous numerics instruction caused an unmasked exception. The address of

the faulty instruction and the address of its operand are stored in the instruction

pointer and data pointer registers. Only Floating-Point and WAIT instructions can

cause this interrupt. The Intel

Quark SoC X1000 Core return address pushed

onto the stack of the exception handler points to a WAIT or Floating-Point

instruction (including prefixes). This instruction can be restarted after clearing the

exception condition in the FPU. The FNINIT, FNCLEX, FNSTSW, FNSTENV, and

FNSAVE instructions can not cause this interrupt.