Specifications

Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 39
System Register Organization—Intel
®
Quark Core
4.0 System Register Organization
4.1 Register Set Overview
The Intel
®
Quark SoC X1000 Core register set can be split into the following
categories:
• Base Architecture Registers
— General Purpose Registers
— Instruction Pointer
— Flags Register
—Segment Registers
• System-Level Registers
— Control Registers
— System Address Registers
• Debug and Test Registers
The base architecture and floating-point registers (see below) are accessible by the
applications program. The system-level registers can only be accessed at privilege level
0 and can only be used by system-level programs. The debug and test registers also
can only be accessed at privilege level 0.
4.2 Floating-Point Registers
In addition to the registers listed above, the Intel
®
Quark SoC X1000 Core has the
following:
• Floating-Point Registers
• Data Registers
•Tag Word
• Status Word
• Instruction and Data Pointers
• Control Word
4.3 Base Architecture Registers
Figure 9 shows the Intel
®
Quark SoC X1000 Core base architecture registers. The
contents of these registers are task-specific and are automatically loaded with a new
context upon a task switch operation.
The base architecture includes six directly accessible descriptors, each specifying a
segment up to 4 Gbytes in size. The descriptors are indicated by the selector values
placed in the Intel
®
Quark SoC X1000 Core segment registers. Various selector values
can be loaded as a program executes.