Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
40 Order Number: 329679-001US
Note: In register descriptions, “set” means “set to 1,” and “reset” means “set to 0.”
Figure 9. Base Architecture Registers
4.3.1 General Purpose Registers
Figure 9 shows the eight 32-bit general purpose registers. These registers hold data or
address quantities. The general purpose registers can support data operands of 1, 8,
16 and 32 bits, and bit fields of 1 to 32 bits. Address operands of 16 and 32 bits are
supported. The 32-bit registers are named EAX, EBX, ECX, EDX, ESI, EDI, EBP and ESP.
A5144-01
Code Segment
Stack Segment
Data Segments
ESP
EBP
EDI
ESI
DLDX EDXDH
CLBX ECXCH
BLBX EBXBH
ALAX
0
2324
1516 78
31
EAXAH
GS
FS
ES
DS
SS
CS
Segment Registers
General Purpose Registers
015
EFLAGS
Flags Register
Instruction Pointer
01516
31
EIPIP
FLAGS