Specifications
Intel
®
Quark SoC X1000 Core
October 2013 Developer’s Manual
Order Number: 329679-001US 41
System Register Organization—Intel
®
Quark Core
The least significant 16 bits of the general purpose registers can be accessed separately
using the 16-bit names of the registers AX, BX, CX, DX, SI, DI, BP and SP. The upper
16 bits of the register are not changed when the lower 16 bits are accessed separately.
Finally, 8-bit operations can individually access the lower byte (bits 7:0) and the
highest byte (bits 15:8) of the general purpose registers AX, BX, CX and DX. The
lowest bytes are named AL, BL, CL and DL, respectively. The higher bytes are named
AH, BH, CH and DH, respectively. The individual byte accessibility offers additional
flexibility for data operations, but is not used for effective address calculation.
4.3.2 Instruction Pointer
The instruction pointer shown in Figure 9 is a 32-bit register named EIP. EIP holds the
offset of the next instruction to be executed. The offset is always relative to the base of
the code segment (CS). The lower 16 bits (bits 15:0) of the EIP contain the 16-bit
instruction pointer named IP, which is used for 16-bit addressing.
4.3.3 Flags Register
The flags register is a 32-bit register named EFLAGS. The defined bits and bit fields
within EFLAGS control certain operations and indicate the status of the Intel
®
Quark
SoC X1000 Core. The lower 16 bits (bit 15:0) of EFLAGS contain the 16-bit register
named FLAGS, which is most useful when executing legacy processor code. Figure 10
shows the EFLAGS register.
EFLAGS bits 1, 3, 5, 15, and 22 to 31 are defined as “Intel Reserved.” When these bits
are stored during interrupt processing or with a PUSHF instruction (push flags onto
stack), a “1” is stored in bit 1 and zeros are stored in bits 3, 5, 15, and 22 to 31.
Figure 10. Flag Registers
A5145-01
012345678910111213141516171819202122232425262728293031
0
EFLAGS
Flags
0
0
IOP
L
N
T
I
D
V
I
P
V
I
F
A
C
V
M
R
F
T
F
S
F
Z
F
A
F
0
P
F
1
C
F
Interrupt Enable
Direction Flag
Overflow
I/O Privilege Level
Nested Task Flag
Resume Flag
Virtual Mode
Alignment Check
Virtual Interrupt Flag
Virtual Interrupt Pending
Identification Flag
O
F
D
F
I
F
Carry Flag
Trap Flag
Sign Flag
Zero Flag
Auxillary Flag
Parity Flag
Indicates Intel Reserved; do not define.
0
Note:
See section 4.2.7 "Compatibility."
Intel Reserved
See Section 4.8 for RESERVED bits.