Specifications

Intel
®
Quark Core—System Register Organization
Intel
®
Quark SoC X1000 Core
Developer’s Manual October 2013
42 Order Number: 329679-001US
ID (Identification Flag, bit 21)
The ability of a program to set and clear the ID flag indicates that the processor
supports the CPUID instruction. Refer to Chapter 12.0, “Instruction Set Summary”
and Appendix C, “Feature Determination.”
VIP (Virtual Interrupt Pending Flag, bit 20)
The VIP flag together with the VIF enable each applications program in a multi-
tasking environment to have virtualized versions of the system's IF flag.
VIF (Virtual Interrupt Flag, bit 19)
The VIF is a virtual image of the IF (interrupt flag) used with VIP.
AC (Alignment Check, bit 18)
The AC bit is defined in the upper 16 bits of the register. It enables the generation
of faults when a memory reference is to a misaligned address. Alignment faults are
enabled when AC is set to 1. A misaligned address is a word access to an odd
address, a dword access to an address that is not on a dword boundary, or an
8-byte reference to an address that is not on a 64-bit word boundary. See Section
10.1.5, “Operand Alignment” on page 192.
Alignment faults are only generated by programs running at privilege level 3. The
AC bit setting is ignored at privilege levels 0, 1, and 2. Note that references to the
descriptor tables (for selector loads), or the task state segment (TSS), are
implicitly level 0 references even when the instructions causing the references are
executed at level 3. Alignment faults are reported through interrupt 17, with an
error code of 0. Table 9 gives the alignment required for the Intel
®
Quark SoC
X1000 Core data types.
Note: Several instructions on the Intel
®
Quark SoC X1000 Core generate misaligned
references, even when their memory address is aligned. For example, on the Intel
®
Quark SoC X1000 Core, the SGDT/SIDT (store global/interrupt descriptor table)
instruction reads/writes two bytes, and then reads/writes four bytes from a “pseudo-
descriptor” at the given address. The Intel
®
Quark SoC X1000 Core generates
misaligned references unless the address is on a 2 mod 4 boundary. The FSAVE and
FRSTOR instructions (floating-point save and restore state) generate misaligned
references for one-half of the register save/restore cycles. The Intel
®
Quark SoC
Table 9. Data Type Alignment Requirements
Memory Access
Alignment
(Byte Boundary)
Word 2
Dword 4
Single Precision Real 4
Double Precision Real 8
Extended Precision Real 8
Selector 2
48-bit Segmented Pointer 4
32-bit Flat Pointer 4
32-bit Segmented Pointer 2
48-bit “Pseudo-Descriptor” 4
FSTENV/FLDENV Save Area 4/2 (On Operand Size)
FSAVE/FRSTOR Save Area 4/2 (On Operand Size)
Bit String 4